1. Technical Field
The present invention relates to phase-locked loops (PLLs) and, in particular, to a PLL lock detector circuit and a method of lock detection.
2. Description of Related Art
PLLs are useful in microprocessors and in the field of mobile communication. When power is turned on, a microprocessor is maintained at a reset state until a voltage controlled oscillation (VCO.) Frequency becomes the same as the normal operation frequency of the microprocessor. That is, the microprocessor is maintained at the reset state until a PLL is locked, to prevent the microprocessor from erroneously operating because of an improper frequency. Apparatuses such as frequency sensitive mobile communication devices use such a microprocessor, so PLLs are particularly essential to these apparatuses.
FIG. 1 is a block diagram illustrating a conventional PLL. The conventional PLL includes a first frequency divider 10, an error signal generator 11, a phase detector circuit 12, a low-pass filter 13, a voltage controlled oscillator 14 and a second frequency divider 15.
The first frequency divider 10 divides a reference frequency XCK by a predetermined number. The second frequency divider 15 divides an output frequency f0 of the voltage controlled oscillator 14 by a predetermined number.
The error signal generator 11 generates an error signal LDI indicating the phase difference between an output signal FR of the first frequency divider 10 and an output signal FN of the second frequency divider 15.
The phase detector circuit 12 compares the frequency and phase of the output signal FR of the first frequency divider 10 with the frequency and phase of the error signal LDI. An output, that is, an error voltage Verr, of the phase detector circuit 12 is an average direct current (DC) voltage proportional to the frequency difference and the phase difference between the output signal, i.e., the lock window signal FR, of the first frequency divider 10 and the output signal, i.e., the signal FN, of the second frequency divider 15.
The low-pass filter 13 removes high frequency components and noise from the error voltage Verr output from the phase detector circuit 12 and determines the dynamic properties of the PLL.
The voltage controlled oscillator 14 adjusts the output frequency f0 thereof such that the error voltage Verr output from the phase detector circuit 12 decreases. The output frequency f0 of the voltage controlled oscillator 14 is usually determined by a value of a pair of devices, that is, a resistor and a capacitor or an inductor and a capacitor, connected to the outside of the voltage controlled oscillator 14.
A PLL lock detector circuit is referred to as a lock condition detector circuit or a phase detector circuit. The PLL lock detector circuit compares the width of a lock window signal, which is arbitrarily set by a designer, with the width of an error signal and determines whether a PLL is locked or unlocked. As a result, a lock or unlock signal is transmitted to a user so that the user can have an advantage in controlling an inner circuit of a larger circuit or in configuring an application circuit or system.
FIG. 2 is a circuit diagram further illustrating the conventional phase detector circuit (a lock detector circuit) shown in FIG. 1. FIG. 3 is a waveform chart illustrating signals corresponding to the operation of the conventional phase detector circuit of FIG. 2.
Referring to FIGS. 2 and 3, a reset signal R initializes a delay (D) flip-flop 20. The conventional phase detector circuit applies a signal XCK/2, obtained by dividing a reference frequency signal by 2, to a control clock terminal CK of the D flip-flop 20 and uses the signal XCK/2 as a lock window signal.
In the conventional phase detector circuit of FIG. 2, the phase of the lock window signal XCK/2 is frequently not the same as that of an error signal LDI. Moreover, since the conventional phase detector circuit detects the state of the error signal LDI only at one edge of the rising and falling edges of the lock window signal, an actually locked PLL may be determined to be unlocked and an actually unlocked PLL may be determined to be locked.